Synopsys jobs - Clackamas, OR
Subscribe to RSS Feed| Posted | Job Title | Company | Location |
|---|---|---|---|
|
More Job Postings from the Web
|
|||
| Jun 01 | Pre-Silicon Validation Engineer | Superior Group | Hillsboro, OR |
|
logic synthesis and timing analysis tools - Synopsys, Synplify Pro. *Minimum 2 years of working experience with FPGA development with proprietary FPGA cards or commercial cards... more |
|||
| Jun 01 | Pre-Silicon Validation Engineer | Kelly Services | Hillsboro, OR |
|
logic synthesis and timing analysis tools - Synopsys, Synplify Pro. 2+ years of working experience with FPGA development with proprietary FPGA cards or commercial cards such as... more |
|||
| Jun 01 | Pre-Silicon Validation Engineer | Experis | Hillsboro, OR |
|
logic synthesis and timing analysis tools - Synopsys, Synplify Pro. 2+ years of working experience with FPGA development with proprietary FPGA cards or commercial cards such as... more |
|||
| May 31 | Pre-Silicon Validation Engineer | Fountain Group | Hillsboro, OR |
|
logic synthesis and timing analysis tools - Synopsys, Synplify Pro. *2+ years of working experience with FPGA development with proprietary FPGA cards or commercial cards such as... more |
|||
| May 30 | Physical Design Engineer | American Cybersystems | Hillsboro, OR |
|
Role & Responsibilities Experience in one of Synopsys ICC/ Magma BlastFusion / Talus / SoC ... Experience with Synopsys, Magma and/or cadence tools... more |
|||
| May 25 | R&D Engineer, Sr Staff | Synopsys | Hillsboro, OR |
|
Responsible for designing, developing, debugging, and maintaining core infrastructure components of a significant new static verification platform. The individual should be... more |
|||
| May 15 | Digital ASIC Designer (Recent Graduate) | HP Careers | Vancouver, WA |
|
development experiences with RTL in Verilog, Synopsys and Primetime tools is preferred. Some familiarity and experiences with programming concepts and languages like C, PERL and... more |
|||
| May 14 | Digital ASIC Designer (Recent Graduate) | HP | Vancouver, WA |
|
development experiences with RTL in Verilog, Synopsys and Primetime tools is preferred. Some familiarity and experiences with programming concepts and languages like C, PERL and... more |
|||
| May 11 | Sr. Asic Design Engineer | Intel | Hillsboro, OR |
|
based VLSI design methodology and relevant Synopsys EDA tools (DC, ICC, PrimeTime). - Demonstrate experience in scripting with Unix shell, Perl and/or Tcl. Preferred Skills: -... more |
|||
| May 08 | Analog Design Engineer - Bsee Verilog Rtl Synopsys Icc | Beaverton, OR | |
|
* Synthesis and Timing analysis experience * Synopsys ICC, DFT tools, scripting in PERL and Shell PREFERRED: * Unix. Communication and team skills JOB DUTIES: * Work with the IP... more |
|||
| Apr 26 | Intern (Technical) | Synopsys | Hillsboro, OR |
|
* Candidate must have 2+years of (educational) experience in the following areas: * Candidate must have 2+years of (educational) experience in the following areas: Interns/Temp more |
|||
| Apr 23 | Device Development Engineer | AMI Semiconductor | Gresham, OR |
|
and wear out mechanisms. .TCAD experience: Synopsys platform preferred. .Layout and DRC experience: Mentor and/or Cadence platforms preferred. .Familiar with Linux and Unix... more |
|||
| Apr 20 | Device Development Engineer | On Semiconductor | Gresham, OR |
|
and wear out mechanisms. TCAD experience: Synopsys platform preferred. Layout and DRC experience: Mentor and/or Cadence platforms preferred. Familiar with Linux and Unix Skilled... more |
|||
| Apr 19 | R&D Engineer, Sr Staff-Timing Analysis | Synopsys | Hillsboro, OR |
|
team and with other product groups at Synopsys globally and across multiple time-zones. In addition, familiarity or experience with any of the following would be a plus: static... more |
|||
| Apr 19 | Regional Nurse Consultant | Executive Search Solutions | Portland, OR |
|
Director of Risk Management Portland, OR We have a new employment opportunity in the Portland Metro / SW Washington area for a RN Risk Manager. This position will require travel... more |
|||
| Apr 16 | Analog Design Engineer | Beaverton, OR | |
|
RTL skills * Experience with DFT technology, Synopsys or Mentor Graphics DFT tools, MBIST and ATPG tools, and scripting in PERL and Shell PREFERRED: * Experience with Unix *... more |
|||
| Apr 16 | Analog Engineer - 298761-PJF | Volt Information Sciences | Hillsboro, OR |
|
Transfer Level, DFT/Design for Test Synopsys/Mentor Graphics DFT Tools, ... following: o Verilog RTL o DFT Technology o Synopsys or Mentor Graphics DFT Tools o MBIST... more |
|||
| Apr 13 | Analog Engineer | Volt Information Sciences | Hillsboro, OR |
|
Transfer Level, DFT/Design for Test Synopsys/Mentor Graphics DFT Tools, ... following: * Verilog RTL * DFT Technology * Synopsys or Mentor Graphics DFT Tools * MBIST... more |
|||
| Apr 12 | Analog Custom Layout/Mask Design Engineer | Idhasoft | Hillsboro, OR |
|
tandard cell Key Responsibilities: Floor planning Layout DRC/LVS verification and fix and implementation Hands-on experience with Cadence/Synopsys EDA tools for custom layout. more |
|||
| Apr 04 | R&D Engineer, Sr I | Synopsys | Hillsboro, OR |
|
Responsible for designing, developing, troubleshooting, or debugging software programs. Develops software tools including operating systems, compilers, routers, networks,... more |
|||
| Mar 12 | Physical Design Engineer | Hiregenics | Portland, OR |
|
Experience with Synopsys, Magma and/or cadence tools ... Magma Blast Fusion/Talus, Blast/Quartz Rail, Synopsys Primetime/Primetime-SI, Synopsys ICC... more |
|||
| Mar 08 | ASIC Design Engineer ( Synopsys) | Mavensoft Technologies | Hillsboro, OR |
|
Years of Experience & Expertise Level: 4 yrs min SR LEVEL BS Project Description: -Laguna PCIe exerciser chip D step. Daily Responsibilities: -ASIC synthesis, layout edits, APR,... more |
|||
| Feb 28 | R&D Engineer, Sr II | Synopsys | Hillsboro, OR |
|
as disseminating application expertise to Synopsys field support engineers to enable them to adapt mask synthesis solutions to customer-specific requirements. MS or PhD in... more |
|||
| Feb 07 | ASIC Design Engineer | Hirevelocity | Hillsboro, OR |
|
based VLSI design methodology and relevant Synopsys EDA tools (DC, ICC, PrimeTime). - Demonstrate experience in scripting with Unix shell, Perl and/or Tcl. Preferred Skills: -... more |
|||
| Nov 09 | Analog Layout Engineer | Idhasoft | Hillsboro, OR |
|
d cells. Responsibilities will include floor planning, DRC/LVS verification and fix, and implementation Hands-on experience with Cadence /Synopsys EDA tools for custom layout. more |
|||
Jobs by 
